Some of the most complicated devices engineered by man are semiconductor integrated circuits. Some circuits such as microprocessors may include a billion transistors or more, and are getting more complicated in their design every year. As a result, testing throughout the design and manufacturing processes is necessary to be able to reliably manufacture these semiconductor integrated circuits. This includes testing of circuit designs, testing of layout designs derived from the circuit designs, and testing of the resulting manufactured integrated circuits.
Static timing analysis (STA) is often utilized for performing timing analysis towards validation and optimization of synchronous circuit designs. This allows the designer to make modifications to improve the reliability, efficiency, and/or speed of the circuit design. Pessimism is generally incorporated into STA so that variations in modeling, design and manufacturing are essentially taken into account.
Graph based analysis (GBA, often also referred to as block-based analysis) is a type of STA used to perform worst case analysis of a circuit over all possible input combinations and all possible paths, but not of the logical operation of the circuit. GBA uses pessimism to improve the speed of the analysis. For example, GBA utilizes the worst input slew of all input pins through each logic element, but not the logic operation of the circuit. Further, graph based analysis has significant pessimism, particularly due to the on-chip variation analysis of the clock network topology.
Path based analysis (PBA) is another type of STA used to calculate delays beginning at the input and tracing the path to the output. It is generally less pessimistic than GBA, but is much slower in analyzing circuit designs as each circuit path is analyzed. For example, only the slews of the input pins along a given circuit path are considered in this analysis. However, path based analysis is most often used to sign-off on the most advanced integrated circuit designs. Because most chips designed and integrated hierarchically, a full flat path based analysis closure and optimization is runtime and resource intensive and often time and cost prohibitive.
Currently, to account for design and manufacture variation effects, STA performs on-chip variation (OCV) analysis with two main approaches: 1) margin based advanced on-chip variation (AOCV); and 2) statistical distribution based parametric on-chip variation analysis (POCV).
With either of these approaches, path-based analysis (PBA) of the block level circuit relies on GBA based context data (such as path depths, distances and latency of the top circuit level clock paths), this introduces pessimism to block level analysis, which can be unbounded in theory. Reducing or resolving this pessimism is a major issue in the design, design planning, analysis, verification and optimization of an integrated circuit.
FIG. 1 is a block diagram of a prior art static timing analysis (STA) diagram 100 illustrating graph based analysis pessimism and path based analysis pessimism in a traditional flat STA and hierarchical STA. There are multiple causes and components in the pessimism in block level PBA analysis. The pessimism usually occurs in block-level register-to-register paths, and also happen for block interface paths. The method described in this document can be employed to resolve or reduce the pessimism for both categories of timing paths. For ease of illustration and description, our focus in this document focus on the block level internal register-to-register paths which is often more important.
The external pessimism may be produced by GBA merging of signal transition or waveforms at convergence points, or by the graph-based derating of latency computed at the top circuit level 102. The most accurate latency in STA is the PBA derated latency. The max_latency of GBA is usually larger than or equal to the max_latency of PBA, which introduces the pessimism at a top circuit level of the hierarchy.
FIG. 1 illustrates this in top circuit level 102. There are two path segments that illustrate this issue in FIG. 1, top circuit level 102 illustrates the external pessimism issue in path segment, S→C→P1, from clock source 104 to common point 106 to clock port 108 and path segment, S→C→P2, from clock source 104 to common point 106 to clock port 110.
The internal pessimism may come from GBA depth level analysis of the top circuit level 102 that is used for block circuit level 112 OCV analysis. The most accurate analysis for the top circuit level used for block circuit level 112 OCV analysis is the PBA depth. This issue is due to the fact that the GBA depth is always less than or equal to the PBA depth. There are three path segments that illustrate this issue in FIG. 1. Block circuit level 112 illustrates the internal pessimism issue in path segment from clock port 1 108 to buffer 114 (P1→B), in path segment from buffer 114 to register 116 (B→R), and in block circuit level 112 path segments from register 116 to clock port 2 110, (P2→R). These block circuit level path segments are illustrative only.
The issue faced by integrated circuit designers is that nearly all circuits are designed hierarchically and are broken into many blocks. Full chip PBA closure and optimization is computationally intensive and cost prohibitive. The ability to close and optimize at a block level or one or more block circuit levels is key for product design quality and design.